1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to efficiently performing timing characterization of regions of an integrated circuit.
2. Description of the Relevant Art
The reduction in geometric dimensions of devices and metal routes on semiconductor chips and the resulting higher integration of functionality on chips has each contributed to an increased effect of manufacturing processing defects and variations. The defects and variations may greatly affect the functionality and performance of on-die circuits. During the manufacturing processing steps, the base layers are inserted in an n-type or a p-type silicon substrate. The base layers include the n-well, p-well, diffusion, and polysilicon layers. Manufacturing defects such as relatively high resistive vias, holes in conductors, mismatches in masks for the base layers, and so forth may cause a given data path to significantly vary from an expected delay. In addition, setup and/or hold time violations may occur creating incorrect results. Stuck-at faults may also occur. In these cases, the integrated circuit (IC) malfunctions. In other cases, such as varying transistor sizes, varying leakage current amounts, and the like, the IC provides correct results, but varies from expected performance.
In one example, a first group of semiconductor wafers are processed in a similar time span by the same equipment. Still, the silicon dies in this first group of wafers may include parameters that vary from expected values due to process variations. The variations across the first group of wafers and within a given wafer for each of these silicon dies may vary in a common manner due to the similar processing conditions. Other silicon dies in a second group of wafers may be processed at another time and/or possibly on other equipment. The parameters for these other dies may vary in a different manner from dies in the first group of wafers due to the different processing conditions. The parameters may include at least leakage current, maximum operating frequency of a clock signal, power consumption, setup and hold times for sequential elements, duty cycle of a clock signal, and threshold voltage.
Dies that are not defective, but provide different measured parameters from expected parameter values may be placed in different bins according to the measured parameters. For example, speed binning may categorize dies based on maximum operational frequency. The IC dies categorized by a given bin may be offered at a different price than IC dies categorized by another bin. In addition, reliably characterizing spatially varying speeds on a given die may allow for tuning of performance-power states on the given die.
Automated test equipment (ATE) has been typically used to provide characterization of the spatially varying parameters on a given die due to process variations. The ATEs are also used to detect any delay defects in on-die tunable delay lines and calibrate them if defects are found. However, ATEs increase testing time and cost. Additionally, the ATEs are used in a test lab at the time of production. Subsequent characterizations of the parameter variations due to at least aging when the die is used over time may not be performed.
In view of the above, efficient methods and mechanisms for efficiently performing timing characterization of regions of an integrated circuit are desired.